The present invention relates to an offset compensation circuit for compensating a DC offset which occurs in a circuit line including an A/D converter or an A/D and D/A converter.
FIG. 1 shows a block diagram of a conventional offset compensation circuit for a circuit line including an A/D converter 1 which changes an analog input signal IN into a digital output signal OUT. The offset compensation circuit includes a most significant bit latch circuit 2 which detects only the polarity bit of the digital output signal OUT from the A/D converter, an integrator 3 which integrates only the polarity bit detected by the most significant bit latch circuit 2 and produces an offset compensation voltage V.sub.CMP, and a filter 4 which band limits the analog input signal IN to allow only a prescribed band of components thereof to pass through the filter 4 and enter into the A/D converter 1. For example, the filter 4 includes an active filter employing an operational amplifier. The offset compensation voltage V.sub.CMP is supplied from the integrator 3 to the input terminal of the operational amplifier to achieve feedback to the circuit line, equalizing the probability of the positive and negative polarities of the digital output signal OUT to each other. As a result, the offset in the digital output signal OUT is automatically compensated by the configuration shown in FIG. 1.
When a music signal shown in FIG. 2(a) is applied as the analog input signal to the circuit line shown in FIG. 1, positive and negative polarity bits shown in FIG. 2(b) are output from the most significant bit latch circuit 2. Since the probability of the positive polarity of the music signal and that of the negative polarity thereof are statistically equal to each other in general, the offset in the digital output signal is compensated by performing feedback using the polarity bits shown in FIG. 2(b). When the analog input signal IN is absent, feedback is performed so that the digital output signal OUT changes between the positive minimum and negative minimum values. However, since the constitution of the conventional offset compensation circuit is such that the most significant bit is detected from the digital output signal to perform the feedback, the operation of the circuit differs depending on the analog input signal. In other words, if the offset is present at the time of absence of the analog input signal, the most significant bit is fixed at the positive or negative polarity to achieve feedback. However, when a sine wave sin (V.sub.IN =A.sub.1 sin.omega.t) with large amplitude as shown in FIG. 3(a) is applied as the analog input signal to the circuit line, the polarity bit (the most significant bit) becomes positive and negative alternately as shown in FIG. 3(b), and a problem occurs that the loop gain of the circuit line and the offset compensation circuit decreases depending on the wave form and amplitude of the input signal. When it is supposed that a 10 mV offset occurs with regard to an input sine wave of 4V.sub.P-P in amplitude, the loop gain of the circuit line and the offset compensation circuit decreases by about 50 dB in comparison with the case where the input signal is absent. Shown in FIG. 3(c) is the polarity bit for an input sine wave (V.sub.IN =A.sub.2 sin.omega.t) of small amplitude. The quantity of the change in the loop gain is determined as ##EQU1## in the cases shown in FIG. 3.
Although the probability of the positive polarity of the music signal and that of the negative polarity thereof are statistically equal to each other in general, they are not always equal to each other within a short period of time. For that reason, it is difficult to set the time constant of the integrator 3. If the time constant of the integrator 3 is set to be small, the response is faster but the offset compensation circuit itself acts to cause an offset depending on the wave form of the music signal within a short period of time. This is because the probabilities of the positive and negative polarities of the sound of a given kind of musical instrument are not equal to each other and as a result the offset compensation circuit operates improperly to produce an output even if the circuit line has no offset.
FIG. 4(a) shows an example of the analog input signal to the circuit line. FIG. 4(b) shows the output signal from the integrator 3. FIG. 4(c) shows the residual offset of the A/D converter 1. When the analog input signal is absent, the level of the offset compensation voltage sent out from the integrator 3 is proper. However, when the music signal is applied as the analog input signal IN to the circuit line, the loop gain decreases as mentioned above, so that the level of the offset compensation voltage drops as shown in FIG. 4(b).
FIG. 5 shows a block diagram of another conventional offset compensation circuit for a circuit line including an A/D and D/A converter 6 which can perform both A/D conversion and D/A conversion. The offset compensation circuit includes an integrator 3 and a filter 4 which are the same as those of the circuit shown in FIG. 1, a switch 5 which is shifted for the A/D conversion or the D/A conversion, a digital detector 7 made of a most significant bit latch circuit which detects only the polarity bit of the digital output signal from the converter 6 as in the offset compensation circuit shown in FIG. 1, and a signal processing section 8 made of a digital signal processor or the like to perform signal processing along with the A/D conversion or the D/A conversion. In the mode of the A/D conversion, the switch 5 is connected at a contact a so that an analog input signal is supplied to the A/D and D/A converter 6 through the filter 4 and changed into the digital output signal by the A/D converting section of the converter. The signal processing section 8 performs necessary processing on the digital signal. The digital signal is supplied to the integrator 3 through the digital detector 7 and integrated so that the integrator sends out an offset compensation voltage V.sub.CMP which is fed back to the filter 4 to compensate an offset in the circuit line. An analog output signal is sent out from the filter to a monitoring output terminal. In the D/A conversion mode, the switch 5 is connected at another contact b, and a digital signal subjected to necessary processing by the signal processing section 8 is changed into an analog signal by the D/A converting section of the A/D and D/A converter 6. The digital signal is supplied to the filter 4 through the contact b of the switch, and a D/A conversion output signal is sent out from the filter 4 to the monitoring output terminal. The digital signal from the signal processing section 8 in this mode is also supplied to the digital detector 7, and the output is supplied to the integrator 3, the output of which is supplied to the filter 4 thus creating feedback. Since the output from the integrator 3 in the D/A mode is determined by digital data applied to the A/D and D/A converter 6 but is independent of the offset voltage in the converter 6, the D/A conversion output signal undergoes a time fluctuation or the like. Although the output from the digital detector 7 can be fixed at a duty factor of 50%, for example, in the D/A conversion mode to cope with the fact that the output from the integrator 3 in this mode is independent of the offset voltage in the converter 6, there is still a problem that the compensation of the offset at the start of the A/D conversion mode is not precisely performed because of the presence of the output from the integrator 3 when the D/A conversion mode is changed to an A/D conversion mode.
FIG. 6(a) shows the mode conversion by the A/D and D/A converter 6. FIG. 6(b) shows the output from the digital detector 7. FIG. 6(c) shows the output from the integrator 3 in the A/D conversion mode and the D/A conversion mode. In the A/D conversion mode, the output from the integrator 3 is the offset compensation voltage based on the polarity bit (most significant bit), for example, obtained by the digital detector 7, and is fed back to compensate the offset. When the offset compensation voltage is positive or negative as shown in FIG. 6(c), the offset in the circuit line has a negative or positive quantity, respectively, equal in magnitude to the offset compensation voltage.
When the A/D and D/A converter is in the D/A conversion mode, a signal of 50% in duty factor is applied to the input terminal of the integrator 3 independently of the digital data. However, even if the duty factor of the signal deviates only slightly from 50%, the output voltage of the integrator 3 rises to a level substantially equal to the voltage of a power supply for an amplifier included in the integrator 3. If the duty factor of the digital data is 50% in that case, the positive and negative magnitudes of the D/A conversion output signal are equal to each other. However, if the duty factor of the digital data deviates even slightly from 50% an error occurs. The output voltage of the integrator 3 drops close to 0 V when a change from the D/A conversion mode to the A/D conversion mode occurs, so that it takes a relatively long time for the integrator 3 to send out a proper offset compensation voltage. For that reason, the compensation of the offset cannot be precisely performed during a period t.sub.1 (shown in FIG. 6(c)) at the start of the A/D conversion mode.
The offset adjustment of the A/D converter 1 shown in FIG. 1 also needs to be performed precisely so that the digital output code is zero in a non-servo state established by opening the feedback loop of the offset compensation circuit and the circuit line. However, the offset compensation circuit is configured so that digital data obtained as a result of the A/D converting action of the A/D converter 1 and the subsequent detecting action of the most significant bit latch circuit 2 are integrated by the integrator 3 to produce the offset compensation voltage V.sub.CMP which is fed back to the circuit line through the analog signal input terminal of the filter 4 to compensate the offset in the A/D converter. For that reason, the feedback loop remains formed at the time of the offset adjustment of the A/D converter 1 so that a servo state is established to ensure the offset is always zero. As a result, it is difficult to precisely perform the offset adjustment of the A/D converter 1.